PEB2256HT datasheet(359/490 Pages) INFINEON

359 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

359

2002-08-27

Receive Control 1 (Read/Write)

Value after reset: 9C

RCO(7:0)

Receive Offset/Receive Frame Marker Offset

Depending on the RP(A to D) pin function different offsets can be

programmed. The SYPR and the RFM pin function cannot be

selected in parallel.

Receive Offset (PC(4:1).RPC(2:0) = 000)

Initial value loaded into the receive bit counter at the trigger edge of

SCLKR when the synchronous pulse on port SYPR is active.

Calculation of delay time T (SCLKR cycles) depends on the value X

of the receive offset register RC(1:0):

system clocking rate: modulo 2.048 MHz (SIC2.SSC2 = 0)

≤ T ≤ 4:X = 4 - T

≤ T ≤ maximum delay:X = 2052 - T

with maximum delay = (256

×SC/SD) -1

with SC = system clock defined by SIC1.SSC(1:0)+SIC2.SSC2

with SD = system data rate

system clocking rate: modulo 1.544 MHz (SIC2.SSC2 = 1)

≤ T ≤ 4:X = 4 - T + (7 × SC/SD)

≤ T ≤ maximum delay :X = (200 × SC/SD) + 4 - T

with maximum delay = 193

×SC/SD - 1

with SC = system clock defined by SIC1.SSC(1:0)+SIC2.SSC2

with SD = system data rate

Delay time T = time between beginning of time slot 0 at RDO and the

initial edge of SCLKR after SYPR goes active.

See page 168 for further description.

RC1

RCO7

RCO5

RCO0

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PEB2256HT Datasheet(PDF) 359 Page - Infineon Technologies AG