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PEB2256HT Datasheet(PDF) 355 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 355 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
T1/J1 Registers
Data Sheet
355
2002-08-27
selected. For proper operation the transmit elastic buffer (2
frames, SIC1.XBS(1:0) = 10) has to be enabled.
SSC2
Select Sync Conditions
Only valid in ESF framing format.
Loss of Frame Alignment FRS0.LFA is declared if more than 320
CRC6 errors per second interval are detected.
Transmit Control 0 (Read/Write)
Value after reset: 00
H
BRM
Enable Bit Robbing Marker
A one in this bit marks the robbed bit positions on the system highway.
RSIGM marks the receive and XSIGM marks the transmit robbed bits.
MFBS
Enable pure Multiframe Begin Signals
Only valid if ESF or F72 format is selected.
0 =
RMFB marks the beginning of every received superframe.
Additional pulses are provided every 12 frames when using
ESF/F24 or F72 format.
1 =
RMFB marks the beginning of every received multiframe.
BRFO
Bit Robbing Force One
Setting this bit forces the robbed bits high transmitted on port RDO.
The received signaling data stream for the signaling controller is not
influenced by this bit.
XCO(10:8)
Transmit Offset
Initial value loaded into the transmit bit counter at the trigger edge of
SCLKX when the synchronous pulse on port SYPX or XMFS is active
Refer to register XC1.
70
XC0
BRM
MFBS
BRFO
XCO10
XCO9
XCO8
(22)



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