PEB2256HT datasheet(356/490 Pages) INFINEON

356 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

356

2002-08-27

Transmit Control 1 (Read/Write)

Value after reset: 9C

A write access to this address resets the transmit elastic buffer to its

basic starting position. Therefore, updating the value should only be

done when the FALC56 is initialized or when the buffer should be

centered. As a consequence a transmit slip will occur.

XCO(7:0)

Transmit Offset

Initial value loaded into the transmit bit counter at the trigger edge of

SCLKX when the synchronous pulse on port SYPX/XMFS is active.

Calculation of delay time T (SCLKX cycles) depends on the value X

of the transmit offset register XC(1:0):

system clocking rate: modulo 2.048 MHz (SIC2.SSC2 = 0)

≤ T ≤ 4: X = 4 - T

≤ T ≤ maximum delay:X = 256 × SC/SD - T + 4)

with maximum delay = (256

× SC/SD) -1

with SC = system clock defined by SIC1.SSC(1:0)+SIC2.SSC2

with SD = 2.048 Mbit/s (system clocking n

× 2.048 MHz)

system clocking rate: modulo 1.544 MHz (SIC2.SSC2 = 1)

≤ T ≤ 4: X = 3 - T + 7 × SC/BF

≤ T ≤ maximum delay:X = 200 × SC/BF - T + 3

with SC = system clock defined by SIC1.SSC(1:0)+SIC2.SSC2

SD = 1.544 Mbit/s (system clocking n

× 1.544 MHz)

with BF = basic frequency = 1.544 MHz

T = Time between the active edge of SCLKX after SYPX pulse begin

and beginning of the next frame (F-bit, channel phase 0), measured

in number of SCLKX clock intervals; maximum delay:

max =(200 × SC/BF)-(7 × SC/BF)-1

See page 178 for further description.

XC1

XCO7

XCO0

(23)

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