PEB2256HT datasheet(381/490 Pages) INFINEON

381 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

381

2002-08-27

Global Configuration Register (Read/Write)

Value after reset: 00H

VIS

Masked Interrupts Visible

0 =

Masked interrupt status bits are not visible in registers ISR(5:0).

1 =

Masked interrupt status bits are visible in ISR(5:0), but they are

not visible in registers GIS.

SCI

Status Change Interrupt

0 =

Interrupts are generated either on activation or deactivation of

the internal interrupt source.

1 =

The following interrupts are activated both on activation and

deactivation of the internal interrupt source:

ISR2.LOS, ISR2.AIS and ISR0.PDEN

SES

Select External Second Timer

0 =

Internal second timer selected

1 =

External second timer selected

ECMC

Error Counter Mode COFA

0 =

Not defined; reserved for future applications.

1 =

A Change of Frame or Multiframe Alignment COFA is detected

since the last resynchronization. The events are accumulated

in the COFA event counter COEC.(1:0).

Multiframe periods received in the asynchronous state are

accumulated in the COFA event counter COEC.(7:2).

An overflow of each counter is disabled.

Power Down

Switches between power-up and power-down mode.

Power up

Power down

All outputs are driven inactive, except the multifunction ports,

which are weakly driven high by the internal pullup devices.

GCR

VIS

SCI

SES

ECMC

(46)

PEB2256HT Datasheet(PDF) 381 Page - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 381 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL