PEB2256HT datasheet(379/490 Pages) INFINEON

379 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

379

2002-08-27

DXSS

DCO-X Synchronization Clock Source

0 =

The DCO-X circuitry synchronizes to the internal reference

clock which is sourced by SCLKX/R or RCLK. Since there are

many reference clock opportunities the following internal

prioritizing in descending order from left to right is realized:

LIM1.RL > CMR1.DXSS > LIM2.ELT > current working clock of

transmit system interface.

If one of these bits is set the corresponding reference clock is

taken.

1 =

DCO-X synchronizes to an external reference clock provided

on pin XP(A to D) pin function TCLK, if no remote loop is active.

TCLK is selected by PC(4:1).XPC(3:0) = 0011

Clock Mode Register 2 (Read/Write)

Value after reset: 00H

DCOXC

DCO-X Center-Frequency Enable

0 =

The center function of the DCO-X circuitry is disabled.

1 =

The center function of the DCO-X circuitry is enabled.

DCO-X centers to 1.544 MHz related to the master clock

reference (MCLK), if reference clock (e.g. SCLKX) is missing.

DCF

DCO-R Center- Frequency Disabled

0 =

The DCO-R circuitry is frequency centered

- in master mode if no 1.544 or 2.048 MHz reference clock on

pin SYNC is provided or

- in slave mode if a loss-of-signal occurs in combination with no

1.544 or 2.048 MHz clock on pin SYNC or

- a gapped clock is provided on pin RCLKI and this clock is

inactive or stopped.

1 =

The center function of the DCO-R circuitry is disabled. The

generated clock (DCO-R) is frequency frozen in that moment

when no clock is available on pin SYNC or pin RCLKI. The

DCO-R circuitry starts synchronization as soon as a clock on

pins SYNC or RCLKI appears.

CMR2

DCOXC

DCF

IRSP

IRSC

IXSP

IXSC

(45)

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