PEB2256HT datasheet(380/490 Pages) INFINEON

380 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

380

2002-08-27

IRSP

Internal Receive System Frame Sync Pulse

0 =

The frame sync pulse for the receive system interface is

sourced by SYPR (if SYPR is applied). If SYPR is not applied,

the frame sync pulse is derived from RDO output signal

internally free running).

The use of IRSP = 0 is recommended.

1 =

The frame sync pulse for the receive system interface is

internally sourced by the DCO-R circuitry. This internally

generated frame sync signal can be output (active low) on

multifunction ports RP(A to D) (RPC(2:0) = 001

B).

Note: This is the only exception where the use of RFM and

SYPR is allowed at the same time. Because only one set of

offset registers (RC1/0) is available, programming is done by

using the SYPR calculation formula in the same way as for the

external SYPR pulse. Bit IRSC must be set for correct

operation.

IRSC

Internal Receive System Clock

0 =

The working clock for the receive system interface is sourced

by SCLKR of or in receive elastic buffer bypass mode from the

corresponding extracted receive clock RCLK.

1 =

The working clock for the receive system interface is sourced

internally by DCO-R or in bypass mode by the extracted receive

clock. SCLKR is ignored.

IXSP

Internal Transmit System Frame Sync Pulse

0 =

The frame sync pulse for the transmit system interface is

sourced by SYPX.

1 =

The frame sync pulse for the transmit system interface is

internally sourced by the DCO-R circuitry. Additionally, the

external XMFS signal defines the transmit multiframe begin.

XMFS is enabled or disabled by the multifunction port

configuration. For correct operation bits CMR2.IXSC/IRSC

must be set. SYPX is ignored.

IXSC

Internal Transmit System Clock

0 =

The working clock for the transmit system interface is sourced

by SCLKX.

1 =

The working clock for the transmit system interface is sourced

internally by the working clock of the receive system interface.

SCLKX is ignored.

PEB2256HT Datasheet(PDF) 380 Page - Infineon Technologies AG

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