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PEB2256HT Datasheet(PDF) 382 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 382 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
T1/J1 Registers
Data Sheet
382
2002-08-27
Errored Second Mask (Read/Write)
Value after reset: FFH
ESM
Errored Second Mask
This register functions as an additional mask register for the interrupt
status bit Errored Second (ISR3.ES). A "1" in a bit position of ESM
deactivates the related second interrupt.
Disable Error Counter (Write)
Value after reset: 00
H
DRBD
Disable Receive Buffer Delay
This bit has to be set before reading the register RBD. It is
automatically reset if RBD has been read.
DCOEC
Disable COFA Event Counter
DBEC
Disable PRBS Bit Error Counter
Only valid if LCR1.EPRM = 1 and FMR1.ECM are reset.
DCEC
Disable CRC Error Counter
DEBC
Disable Errored Block Counter
DCVC
Disable Code Violation Counter
DFEC
Disable Framing Error Counter
These bits are only valid if FMR1.ECM is cleared. They have to be set
before reading the error counters. They are reset automatically if the
corresponding error counter high byte has been read. With the rising
edge of these bits the error counters are latched and then cleared.
Note: Error counters and receive buffer delay can be read 1 µs after setting the
according bit in bit DEC.
70
ESM
LFA
FER
CER
AIS
LOS
CVE
SLIP
(47)
70
DEC
DRBD
DCOEC
DBEC
DCEC
DEBC
DCVC
DFEC
(60)



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