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PEB2256HT Datasheet(PDF) 395 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 395 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
T1/J1 Registers
Data Sheet
395
2002-08-27
AFX
Automatic FISU Transmission - HDLC Channel 1
After the contents of the transmit FIFO (XFIFO) has been transmitted
completely, FISUs are transmitted automatically. These FISUs
contain the FSN and BSO of the last transmitted signaling unit
(provided in XFIFO).
0 =
Automatic FISU transmission disabled.
1 =
Automatic FISU transmission enabled.
CR
Command Response - HDLC Channel 1
Reflects the status of the CR bit in the SAPI octet transmitted during
Periodical Performance Report (PPR), if CCR5.EPR = 1.
0=
CR bit= 0
1=
CR bit= 1
EPR
Enable Periodical Performance Report (PPR) - HDLC Channel 1
If the periodical performance report is to be used, an HDLC format
must be selected by MODE.MDS(2:0).
0 =
PPR disabled.
1 =
PPR enabled.
Mode Register 2 (Read/Write)
Value after reset: 00
H
MDS2(2:0)
Mode Select - HDLC Channel 2
The operating mode of the HDLC controller is selected.
000
=Reserved
001
=Reserved
010
=One-byte address comparison mode (RAL1, 2)
011
=Two-byte address comparison mode (RAH1, 2 and RAL1, 2)
100
=No address comparison
101
=One-byte address comparison mode (RAH1, 2)
110
=Reserved
111
=No HDLC framing mode 1
70
MODE2
MDS22
MDS21
MDS20
HRAC2
DIV2
(8E)



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