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PEB2256HT Datasheet(PDF) 391 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 391 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
T1/J1 Registers
Data Sheet
391
2002-08-27
XHF3
Transmit HDLC Frame - HDLC Channel 3
After having written up to 32 bytes to the XFIFO3, this command
initiates the transmission of a HDLC frame.
XTF3
Transmit Transparent Frame - HDLC Channel 3
Initiates the transmission of a transparent frame without HDLC
framing.
XME3
Transmit Message End - HDLC Channel 3
Indicates that the data block written last to the XFIFO3 completes the
current frame. The FALC
® can terminate the transmission operation
properly by appending the CRC and the closing flag sequence to the
data.
SRES3
Signaling Transmitter Reset - HDLC Channel 3
The transmitter of the signaling controller is reset. XFIFO3 is cleared
of any data and an abort sequence (seven 1s) followed by interframe
time fill is transmitted. In response to SRES3 an XPR3 interrupt is
generated.
This command can be used by the CPU to abort a frame currently in
transmission.
Common Configuration Register 3 (Read/Write)
Value after reset: 00
H
RADD2
Receive Address Pushed to RFIFO2
If this bit is set, the received HDLC channel 2 address information (1
or 2 bytes, depending on the address mode selected via
MODE2.MDS02) is pushed to RFIFO2. This function is applicable in
non-auto mode and transparent mode 1.
70
CCR3
RADD2
RCRC2
XCRC2
ITF2
XMFA2
RFT12
RFT02
(8B)



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