PEB2256HT datasheet(125/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Functional Description T1/J1

Data Sheet

125

2002-08-27

• Detection:

An alarm is generated if the incoming data stream has no pulses (no transitions) for a

certain number (N) of consecutive pulse periods. “No pulse” in the digital receive

interface means a logical zero on pins RDIP/RDIN or ROID. A pulse with an amplitude

less than Q dB below nominal is the criteria for “no pulse” in the analog receive

interface (LIM1.DRS = 0). The receive signal level Q is programmable by three control

bits LIM1.RIL(2:0) (see Chapter 11.3 on page 447). The number N is set by an 8 bit

the number of pulse periods, i.e. the time which has to suspend until the alarm has to

be detected. The programmable range is 16 to 4096 pulse periods.

• Recovery:

In general the recovery procedure starts after detecting a logical "1" (digital receive

interface) or a pulse (analog receive interface) with an amplitude more than Q dB

(defined by LIM1.RIL(2:0)) of the nominal pulse. The value in the 8 bit register PCR

defines the number of pulses (1 to 255) to clear the LOS alarm. Additional recovery

conditions are programmed by register LIM2.

If a loss-of-signal condition is detected in long-haul mode, the data stream can optionally

be cleared automatically to avoid bit errors before LOS is indicated. The selection is

done by LIM1.CLOS = 1.

5.1.9

Receive Jitter Attenuator (T1/J1)

The receive jitter attenuator is placed in the receive path. The working clock is an

internally generated high frequency clock based on the clock provided on pin MCLK. The

jitter attenuator meets the requirements of PUB 62411, PUB 43802, TR-TSY 009,TR-

TSY 253, TR-TSY 499 and ITU-T I.431, G.703 and G. 824.

The internal PLL circuitry DCO-R generates a "jitter-free" output clock which is directly

depending on the phase difference of the incoming clock and the jitter attenuated

clock.The receive jitter attenuator can be synchronized either on the extracted receive

clock RCLK or on a 1.544-, 2.048-MHz or 8-kHz clock provided on pin SYNC (8 kHz in

master mode only). The received data is written into the receive elastic buffer with RCLK

and are read out with the de-jittered clock sourced by DCO-R. The jitter attenuated clock

can be output on pins RCLK, CLK1 or SCLKR. Optionally an 8-kHz clock is provided on

pin SEC/FSC.

The DCO-R circuitry attenuates the incoming jittered clock starting at 6-Hz jitter

frequency with 20 dB per decade fall-off. Wander with a jitter frequency below 6 Hz is

passed unattenuated. The intrinsic jitter in the absence of any input jitter is < 0.02 UI.

For some applications it might be useful starting of jitter attenuation at lower frequencies.

Therefore the corner frequency is switchable by the factor of ten down to 0.6 Hz

(LIM2.SCF).

The DCO-R circuitry is automatically centered to the nominal bit rate if the reference

clock on pin SYNC/RCLK is missed for 2, 3 or 4 of the 2.048-MHz or 1.544-MHz clock

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