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PEB2256HT Datasheet(PDF) 129 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 129 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
Functional Description T1/J1
Data Sheet
129
2002-08-27
5.1.11
Output Jitter (T1/J1)
According to the input jitter defined by PUB62411 the FALC56 generates the output jitter,
which is specified in Table 29 below.
5.1.12
Framer/Synchronizer (T1/J1)
The following functions are performed:
• Synchronization on pulse frame and multiframe
• Error indication when synchronization is lost. In this case, AIS is sent to the system
side automatically and remote alarm to the remote end if enabled.
• Initiating and controlling of resynchronization after reaching the asynchronous state.
This is done automatically by the FALC56 or user controlled by the microprocessor
interface.
• Detection of remote alarm (yellow alarm) indication from the incoming data stream.
• Separation of service bits and data link bits. This information is stored in special status
registers.
• Detection of framed or unframed in-band loop-up/-down code
• Generation of various maskable interrupt statuses of the receiver functions.
• Generation of control signals to synchronize the CRC checker, and the receive elastic
buffer.
If programmed and applicable to the selected multiframe format, CRC checking of the
incoming data stream is done by generating check bits for a CRC multiframe according
to the CRC6 procedure (refer to ITU-T G.704). These bits are compared with those
check bits that are received during the next CRC multiframe. If there is at least one
mismatch, the CRC error counter (16 bit) is incremented.
5.1.13
Receive Elastic Buffer (T1/J1)
The received bit stream is stored in the receive elastic buffer. The memory is organized
as a two-frame elastic buffer with a maximum size of 2
× 193 bit. The size of the elastic
buffer is configured independently for the receive and transmit direction. Programming
of the receive buffer size is done by SIC1.RBS1/0:
Table 29
Output Jitter (T1/J1)
Specification
Measurement Filter Bandwidth
Output Jitter
(UI peak to peak)
Lower Cutoff
Upper Cutoff
PUB 62411
10 Hz
8 kHz
< 0.015
8 kHz
40 kHz
< 0.015
10 Hz
40 kHz
< 0.015
Broadband
< 0.02



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