Electronic Components Datasheet Search
  English  ▼

X  

PEB2256HT Datasheet(PDF) 132 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 132 Page - Infineon Technologies AG

Back Button PEB2256HT Datasheet HTML 128Page - Infineon Technologies AG PEB2256HT Datasheet HTML 129Page - Infineon Technologies AG PEB2256HT Datasheet HTML 130Page - Infineon Technologies AG PEB2256HT Datasheet HTML 131Page - Infineon Technologies AG PEB2256HT Datasheet HTML 132Page - Infineon Technologies AG PEB2256HT Datasheet HTML 133Page - Infineon Technologies AG PEB2256HT Datasheet HTML 134Page - Infineon Technologies AG PEB2256HT Datasheet HTML 135Page - Infineon Technologies AG PEB2256HT Datasheet HTML 136Page - Infineon Technologies AG Next Button
Zoom Inzoom in Zoom Outzoom out
 132 / 490 page
background image
FALC56 V1.2
PEB 2256
Functional Description T1/J1
Data Sheet
132
2002-08-27
Figure 47 gives an idea of operation of the receive elastic buffer:
A slip condition is detected when the write pointer (W) and the read pointer (R) of the
memory are nearly coincident, i.e. the read pointer is within the slip limits (S +, S –). If a
slip condition is detected, a negative slip (one frame or one half of the current buffer size
is skipped) or a positive slip (one frame or one half of the current buffer size is read out
twice) is performed at the system interface, depending on the difference between RCLK
and the current working clock of the receive backplane interface, i.e. on the position of
pointer R and W within the memory. A positive/negative slip is indicated by the interrupt
status bits ISR3.RSP and ISR3.RSN.
Table 31
Receive Buffer Operation Modes (T1/J1)
Buffer Size
(SIC1.RBS1/0)
TS Offset program.
(RC1/0) + SYPR = input
Slip perform.
bypass
1)
1)
In bypass mode the clock provided on pin SCLKR is ignored. Clocking is done with RCLK.
disabled
no
short buffer
not recommended,
recommended:
SYPR = output
yes
1 frame
not recommended,
recommended:
SYPR = output
yes
2 frames
enabled
yes



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com