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PEB2256HT Datasheet(PDF) 131 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 131 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
Functional Description T1/J1
Data Sheet
131
2002-08-27
The 24 received time slots (T1/J1) can be translated into the 32 system time slots (E1)
in two different channel translation modes (FMR1.CTM). Unequipped time slots are set
to FF
H. See Table 30.
– : FF
H
In one frame or short buffer mode the delay through the receive buffer is reduced to an
average delay of 96 or 48 bits. In bypass mode the time slot assigner is disabled. In this
case SYPR programmed as input is ignored. Slips are performed in all buffer modes
except the bypass mode. After a slip is detected the read pointer is adjusted to one half
of the current buffer size.
The following table gives an overview of the receive buffer operating mode.
Table 30
Channel Translation Modes (DS1/J1)
Channels
Time Slots
Channels
Time Slots
Channel
Translation
Mode 0
Channel
Translation
Mode 1
Channel
Translation
Mode 0
Channel
Translation
Mode 1
FS/DL
FS/DL
0
–
16
16
11
1
13
17
17
22
2
14
18
18
33
3
15
19
19
–
44
–
20
20
45
5
16
21
21
56
6
17
22
22
67
7
18
23
23
–
88
–
24
24
79
9
19
–
25
810
10
20
–
26
911
11
21
–
27
–
12
12
––
28
10
13
13
22
–
29
11
14
14
23
–
30
12
15
15
24
–
31



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