PEB2256HT datasheet(130/490 Pages) INFINEON

130 / 490 page

FALC56 V1.2

PEB 2256

Functional Description T1/J1

Data Sheet

130

2002-08-27

• RBS1/0 = 00: two frame buffer or 386 bits

Maximum of wander amplitude (peak-to-peak): (1 UI = 648 ns)

System interface clocking rate: modulo 2.048 MHz:

142 UI in channel translation mode 0

78 UI in channel translation mode 1

System interface clocking rate: modulo 1.544 MHz:

Maximum of wander: 140 UI

average delay after performing a slip: 1 frame or 193 bits

• RBS1/0 = 01: one frame buffer or 193 bits

System interface clocking rate: modulo 2.048 MHz:

Maximum of wander: 70 UI in channel translation mode 0

Maximum of wander: 50 UI in channel translation mode 1

System interface clocking rate: modulo 1.544 MHz:

Maximum of wander: 74 UI

average delay after performing a slip: 96 bits

• RBS1/0 = 10: short buffer or 96 bits

System interface clocking rate: modulo 2.048 MHz:

Maximum of wander: 28 UI in channel translation mode 0; channel translation mode

1 not supported

System interface clocking rate: modulo 1.544 MHz:

Maximum of wander: 38 UI

average delay after performing a slip: 48 bits

• RBS1/0 = 11: Bypass of the receive elastic buffer

The functions are:

• Clock adaption between system clock (SCLKR) and internally generated route clock

(RCLK).

• Compensation of input wander and jitter.

• Frame alignment between system frame and receive route frame

• Reporting and controlling of slips

Controlled by special signals generated by the receiver, the unipolar bit stream is

converted into bit-parallel, time slot serial data which is circularly written to the elastic

buffer using internally generated Receive Route Clock (RCLK).

Reading of stored data is controlled by the system clock sourced by SCLKR or by the

receive jitter attenuator and the synchronization pulse (SYPR) together with the

programmed offset values for the receive time slot/clock slot counters. After conversion

into a serial data stream, the data is sent out on port RDO. If the receive buffer is

bypassed programming of the time slot offset is disabled and data is clocked off with

RCLK instead of SCLKR.

PEB2256HT Datasheet(PDF) 130 Page - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 130 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL