PEB2256HT datasheet(126/490 Pages) INFINEON

126 / 490 page

FALC56 V1.2

PEB 2256

Functional Description T1/J1

Data Sheet

126

2002-08-27

periods. This center function of DCO-R can be optionally disabled (CMR2.DCF = 1) in

order to accept a gapped reference clock.

In analog line interface mode the RCLK is always running. Only in digital line interface

mode with single-rail data (NRZ) a gapped clock on pin RCLK can occur.

The receive jitter attenuator works in two different modes:

• Slave mode

In slave mode (LIM0.MAS = 0) the DCO-R is synchronized on the recovered route

clock. In case of LOS the DCO-R switches automatically to master mode. If bit

CMR1.DCS is set automatic switching from RCLK to SYNC is disabled.

• Master mode

In master mode (LIM0.MAS = 1) the jitter attenuator is in free running mode if no clock

is supplied on pin SYNC. If an external clock on the SYNC input is applied, the DCO-

R synchronizes to this input. The external frequency can be 1.544 MHz

(LIM1.DCOC = 0; IPC.SSYF = 0), 2.048 MHz (LIM1.DCOC = 1; IPC.SSYF = 0) or 8.0

kHz (IPC.SSYF = 1; LIM1.DCOC = don’t care).

The following table shows the clock modes with the corresponding synchronization

sources.

Table 28

System Clocking (T1/J1)

Mode

Internal

LOS Active

SYNC

Input

System Clocks

Master

independent Fixed to

DCO-R centered, if CMR2.DCF = 0.

(CMR2.DCF should not be set)

Master

independent 1.544 MHz Synchronized on SYNC input (external

1.544 MHz, IPC.SSYF = 0, LIM1.DCOC = 0)

Master

independent 2.048 MHz Synchronized on SYNC input (external

2.048 MHz, IPC.SSYF = 0, LIM1.DCOC = 1)

Master

independent 8.0 kHz

Synchronized on SYNC input (external 8.0 kHz,

IPC.SSYF = 1, CMR2.DCF = 0)

Slave

Fixed to

Synchronized on line RCLK

Slave

1.544 or

2.048 MHz

Synchronized on line RCLK

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