PEB2256HT datasheet(134/490 Pages) INFINEON

134 / 490 page

FALC56 V1.2

PEB 2256

Functional Description T1/J1

Data Sheet

134

2002-08-27

5.1.14

Receive Signaling Controller (T1/J1)

The signaling controller can be programmed to operate in various signaling modes. The

FALC56 performs the following signaling and data link methods.

5.1.14.1

HDLC or LAPD access

The FALC56 offers three independent HDLC channels. All of them provide the following

features:

• 64 byte receive FIFO for each channel

• 64 byte transmit FIFO for each channel

• transmission in one of 24 time slots

(time slot number programmable for each channel individually)

• transmission in even frames only, odd frames only or both

(programmable for each channel individually)

• bit positions to be used in selected time slots are maskable

(any bit position can be enabled for each channel individually)

• HDLC or transparent mode

• flag detection

• CRC checking

• bit-stuffing

• flexible address recognition (1 byte, 2 bytes)

• C/R bit processing (according to LAPD protocol)

In addition to this, HDLC channel 1 provides:

• SS7 support

• BOM (bit oriented message) support

• flexibility to insert and extract data during certain time slots, any combination of time

slots can be programmed independently for the receive and transmit direction

In case of common channel signaling the signaling procedure HDLC/SDLC or LAPD

according to Q.921 is supported. The signaling controller of the FALC56 performs the

flag detection, CRC checking, address comparison and zero bit removing. The received

data flow and the address recognition features can be performed in very flexible way, to

satisfy almost any practical requirements. Depending on the selected address mode, the

FALC56 performs a 1 or 2-byte address recognition. If a 2-byte address field is selected,

the high address byte is compared with the fixed value FEH or FCH (group address) as

well as with two individually programmable values in RAH1 and RAH2 registers.

According to the ISDN LAPD protocol, bit 1 of the high byte address is interpreted as

command/response bit (C/R) and is excluded from the address comparison. Buffering of

receive data is done in a 64 byte deep RFIFO.

In signaling controller transparent mode, fully transparent data reception without HDLC

PEB2256HT Datasheet(PDF) 134 Page - Infineon Technologies AG

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