PEB2256HT datasheet(145/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Functional Description T1/J1

Data Sheet

145

2002-08-27

5.2.6.1

Synchronization Procedures

For multiframe synchronization the FAS-bits are observed. Synchronous state is

reached if at least one framing candidate is definitely found, or the synchronizer is forced

to lock onto the next available candidate (FMR0.FRS).

In the synchronous state the framing bits (FAS-bits) are observed. The following

conditions selected by FMR4.SSC1/0 lead to the asynchronous state:

• two errors within 4/5/6 framing bits

• two or more erroneous framing bits within one ESF multiframe

• more than 320 CRC6 errors per second interval (FMR5.SSC2)

• 4 incorrect (1 out of 6) consecutive multiframes independent of CRC6 errors.

There are four multiframe synchronization modes selectable using FMR2.MCSP and

FMR2.SSP.

• FMR2.MCSP/SSP = 00: In the synchronous state, the setting of FMR0.FRS or

FMR0.EXLS resets the synchronizer and initiates a new frame search. The

synchronous state is reached again, if there is only one definite framing candidate. In

the case of repeated apparent simulated candidates, the synchronizer remains in the

asynchronous state.

In asynchronous state, setting bit FMR0.FRS induces the synchronizer to lock onto

the next available framing candidate if there is one. At the same time the internal

framing pattern memory is cleared and other possible framing candidates are lost.

• FMR2.MCSP/SSP = 01: Synchronization is achieved when 3 consecutive multiframe

pattern are correctly found independent of the occurrence of CRC6 errors. If only one

or two consecutive multiframe pattern were detected the FALC56 stays in the

asynchronous state, searching for a possible additionally available framing pattern.

This procedure is repeated until the framer has found three consecutive multiframe

pattern in a row.

• FMR2.MCSP/SSP = 10: This mode has been added in order to be able to choose

multiple framing pattern candidates step by step. I.e. if in synchronous state the CRC

error counter indicates that the synchronization might have been based on an alias

framing pattern, setting of FMR0.FRS leads to synchronization on the next candidate

available. However, only the previously assumed candidate is discarded in the internal

framing pattern memory. The latter procedure can be repeated until the framer has

locked on the right pattern (no extensive CRC errors).

The synchronizer is reset completely and initiates a new frame search, if there is no

multiframing found. In this case bit FRS0.FSRF toggles.

• FMR2.MCSP/SSP = 11: Synchronization including automatic CRC6 checking

Synchronization is achieved when framing pattern are correctly found and the CRC6

checksum is received without an error. If the CRC6 check failed on the assumed

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