PEB2256HT datasheet(162/490 Pages) INFINEON

162 / 490 page

FALC56 V1.2

PEB 2256

Functional Description T1/J1

Data Sheet

162

2002-08-27

In external signaling mode the signaling data is sampled with the working clock of the

transmit system interface (SCLKX) together with the transmit synchronous pulse

(SYPX). Data on XSIG is latched in the bit positions 5 to 8 per time slot, bits 1 to 4 are

ignored. The FS/DL-bit is sampled on port XSIG and inserted in the outgoing data

stream. The received CAS multiframe is inserted frame aligned into the data stream on

XDI. Data sourced by the internal signaling controller overwrites the external signaling

data which must be valid during the last frame of a multiframe.

Internal multiplexing of data and signaling data can be disabled on a per time slot basis

(clear channel capability). This is also valid when using the internal and external

signaling mode.

5.4.7.4

CAS Bit-Robbing (T1/J1, µP access mode)

The signaling controller inserts the bit stream either on the transmit line side or if external

signaling is enabled on the transmit system side. Signaling data is sourced internally

from registers XS(12:1).

Internal multiplexing of data and signaling data can be disabled on a per time slot basis

(clear channel capability). This is also valid when using the internal and external

signaling mode.

5.4.7.5

Data Link Access in ESF/F24 and F72 Format (T1/J1)

The DL-channel protocol is supported as follows:

• access is done on a multiframe basis through registers XDL(3:1) or

• HDLC access or transparent transmission (non HDLC mode) from XFIFO (HDLC

channel 1 only)

The signaling information stored in the XFIFO is inserted in the DL-bits of frame 26 to 72

in F72 format or in every other frame in ESF format. Transmission can be done on a

multiframe boundary (CCR1.XMFA = 1). Operating in HDLC or BOM mode “flags” or

“idle” are transmitted as interframe timefill.

5.4.7.6

Periodical Performance Report in ESF Format (T1/J1)

According to ANSI T1.403 the FALC56 can automatically generate the Periodical

Performance Report (PPR) and transmit it every second in the data link channel of the

extended superframe format (ESF/F24 only). Automatic sending of this report can be

enabled/disabled by the use of bit CCR5.EPR. A single report can be initiated manually

at any time (by setting CMDR2.XPPR = 1).

Performance information is sampled every second and the report contains data of the

last four seconds as shown in the following tables.

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