PEB2256HT datasheet(161/490 Pages) INFINEON

161 / 490 page

FALC56 V1.2

PEB 2256

Functional Description T1/J1

Data Sheet

161

2002-08-27

HDLC framing is performed. Optionally the FALC56 supports the continuous

transmission of the XFIFO contents.

Operating in HDLC or BOM mode “flags” or “idle” are transmitted as interframe timefill.

The FALC56 offers the flexibility to insert data during certain time slots. Any

combinations of time slots can be programmed separately for the receive and transmit

direction if using HDLC channel 1. HDLC channel 2 and 3 support one programmable

time slot common for receive and transmit direction each.

5.4.7.2

Support of Signaling System #7

The HDLC controller of channel 1 supports the signaling system #7 (SS7) which is

described in ITU-Q.703. The following description assumes, that the reader is familiar

with the SS7 protocol definition.

SS7 support must be activated by setting the MODE register. Data stored in the transmit

FIFO (XFIFO) is sent automatically. The SS7 protocol is supported by the following

hardware features in transmit direction:

• transmission of flags at the beginning of each Signaling Unit

• bit stuffing (zero insertion)

• calculation of the CRC16 checksum:

The transmitter adds the checksum to each Signaling Unit.

Each signaling unit written to the transmit FIFO (XFIFO, 2

×32 bytes) is sent once or

repeatedly including flags, CRC checksum and stuffed bits. After e.g. an MSU has

been transmitted completely, the FALC56 optionally starts sending of FISUs

containing the forward sequence number (FSN) and the backward sequence number

(BSN) of the previously transmitted signaling unit. Setting bit CCR5.AFX causes Fill

In Signaling Units (FISUs) to be sent continuously, if no HDLC or Signaling Unit (SU)

is to be transmitted from XFIFO. During update of XFIFO, automatic transmission is

interrupted and resumed after update is completed. The internally generated FISUs

contain FSN and BSN of the last transmitted signaling unit written to XFIFO.

Using CMDR.XREP = 1, the contents of XFIFO can be sent continuously. Clearing of

CMDR.XRES/SRES stops the automatic repetition of transmission. This function is

also available for HDLC frames, so no flag generation, CRC byte generation and bit

stuffing is necessary.

Example: After an MSU has been sent repetitively and XREP has been cleared,

FISUs are sent automatically.

5.4.7.3

CAS Bit-Robbing (T1/J1, serial mode)

The signaling controller inserts the bit stream either on the transmit line side or if external

signaling is enabled on the transmit system side. Signaling data is sourced on port XSIG,

which is selected by register PC(4:1) and FMR5.EIBR = 1.

PEB2256HT Datasheet(PDF) 161 Page - Infineon Technologies AG

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