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PEB2256HT Datasheet(PDF) 157 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 157 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
Functional Description T1/J1
Data Sheet
157
2002-08-27
Figure 52
Transmit Clock System (T1/J1)
Note: DR = Dual-Rail interface
DCO-X Digital Controlled Oscillator transmit
5.4.4
Transmit Elastic Buffer (T1/J1)
The transmit elastic store with a size of max. 2
× 193 bit (two frames) serves as a
temporary store for the PCM data to adapt the system clock (SCLKX) to the internally
generated clock for the transmit data, and to retranslate time slot structure used in the
system to that of the line side. Its optimal start position is initiated when programming the
transmit time slot offset values. A difference in the effective data rates of system side and
transmit side lead to an overflow or underflow of the transmit memory. Thus, errors in
data transmission to the remote end occur. This error condition (transmit slip) is reported
to the microprocessor by interrupt status registers.
The received bit stream from pin XDI is optionally stored in the transmit elastic buffer.
The memory is organized as the receive elastic buffer. Programming of the transmit
buffer size is done by SIC1.XBS1/0:
• XBS1/0 = 00: bypass of the transmit elastic buffer
• XBS1/0 = 01: one frame buffer or 193 bits
Maximum of wander amplitude (peak-to-peak): (1 UI = 648 ns)
System interface clocking rate: modulo 2.048 MHz:
ITS10305
Pulse Shaper
D
Jitter
Framer
SCLKX
XL1/
XDOP/
XL2/
XDON
XCLK
A
XOID
DR
DR
Elastic
Store
XDI
RCLK
TCLK
Transmit
Attenuator
DCO-X
SCLKR
Internal Clock of
Receive System
TCLK
÷ 4
Clocking
Unit
MCLK
(E1: 8MHz)
Interface
Transmit
(T1: 6MHz)
E1: 8MHz
T1: 6MHz



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