PEB2256HT datasheet(153/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Functional Description T1/J1

Data Sheet

153

2002-08-27

5.3.6

Clear Channel Capability

For support of common T1 applications, clear channels can be specified through the 3-

byte register bank CCB(1:3). In this mode the contents of selected transmit time slots are

not overwritten by internally or externally sourced bit-robbing and zero code suppression

(B7 stuffing) information.

5.3.7

In-Band Loop Generation and Detection

The FALC56 generates and detects a framed or unframed in-band loop-up (activate,

00001) and loop-down (deactivate, 001) pattern according to ANSI T1.403 with bit error

rates as high as 10

-2. Framed or unframed in-band loop code is selected by LCR1.FLLB.

Replacing the in-band loop codes with transmit data is done by FMR5.XLD/XLU.

The FALC56 also offers the ability generating and detecting of a flexible in-band loop-up

and -down pattern (LCR1.LLBP = 1). The loop-up and loop-down pattern is individually

programmable from 2 to 8 bits in length (LCR1.LAC1/0 and LCR1.LDC1/0).

Programming of loop codes is done in registers LCR2 and LCR3.

Status and interrupt status bits inform the user whether loop-up or loop-down code was

detected.

5.3.8

Transparent Mode

The transparent modes are useful for loop-backs or for routing data unchanged through

the FALC56.

In receive direction, transparency for ternary or dual-/single-rail unipolar data is always

achieved if the receiver is in the synchronous state. All bits in F-bit position of the

incoming multiframe are forwarded to RDO and inserted in the FS/DL time slot or in the

F-bit position. In asynchronous state the received data is switched through transparently

if bit FMR2.DAIS is set. Setting of bit LOOP.RTM disconnects control of the elastic buffer

from the receiver. The elastic buffer is now in a “free running” mode without any

possibility to update the time slot assignment to a new frame position in case of

resynchronization of the receiver. Together with FMR2.DAIS this function is used to

realize undisturbed transparent reception.

Setting bit FMR4.TM switches the FALC56 in transmit transparent mode:

In transmit direction bit 8 of the FS/DL time slot from the system highway (XDI) is inserted

in the F-bit position of the outgoing frame. For complete transparency the internal

signaling controller, idle code generation, AIS alarm generation, single channel and

payload loop-back has to be disabled and cleared channels have to be defined by

registers CCB1

…3.

5.3.9

Pulse-Density Detection

The FALC56 examines the receive data stream on the pulse-density requirement which

is defined by ANSI T1. 403. More than 14 consecutive zeros or less than N ones in each

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