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PEB2256HT Datasheet(PDF) 183 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 183 Page - Infineon Technologies AG |
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183 / 490 page  FALC56 V1.2 PEB 2256 Functional Description T1/J1 Data Sheet 183 2002-08-27 5.6.3 Payload Loop-Back To perform an effective circuit test a line loop is implemented. If the payload loop-back (FMR2.PLB) is activated the received 192 bits of payload data is looped back to the transmit direction. The framing bits, CRC6 and DL-bits are not looped, if FMR4.TM = 0. They are originated by the FALC56 transmitter. If FMR4.TM = 1 the received FS/DL-bit is sent transparently back to the line interface. Following pins are ignored: XDI, XSIG, TCLK, SCLKX, SYPX and XMFS. All the received data is processed normally. With bit FMR2.SAIS an AIS can be sent to the system interface on pin RDO. Figure 73 Payload Loop (T1/J1) ITS09748 Clock + Data Rec. Framer Elast. Store Trans. Framer RDO XDI RCLK RL1 RL2 XL1 XL2 Recovery SCLKX SCLKR MUX AIS-GEN Elast. Store |
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