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PEB2256HT Datasheet(PDF) 185 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 185 Page - Infineon Technologies AG |
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185 / 490 page ![]() FALC56 V1.2 PEB 2256 Functional Description T1/J1 Data Sheet 185 2002-08-27 5.6.5 Single Channel Loop-Back (loop-back of time slots) The channel loop-back is selected by LOOP.ECLB = 1. Each of the 24 time slots can be selected for loop-back from the system PCM input (XDI) to the system PCM output (RDO). This loop-back is programmed for one time slot at a time selected by register LOOP. During loop-back, an idle channel code programmed in register IDLE is transmitted to the remote end in the corresponding PCM route time slot. For the time slot test, sending sequences of test patterns like a 1-kHz check signal should be avoided. Otherwise an increased occurrence of slips in the tested time slot disturbs testing. These slips do not influence the other time slots and the function of the receive memory. The usage of a quasi-static test pattern is recommended. Figure 75 Channel Loop-Back (T1/J1) ITS09747 RDO XDI RCLK RL1 RL2 XL1 XL2 IDLE Code Framer Trans. Framer Rec. Store Elast. Store Elast. MUX MUX Recovery Data Clock + |
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