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PEB2256HT Datasheet(PDF) 189 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 189 Page - Infineon Technologies AG |
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189 / 490 page  FALC56 V1.2 PEB 2256 Operational Description E1 Data Sheet 189 2002-08-27 LOOP XSW XSP TSWM 00 H 00 H 00 H 00 H Channel loop-back and single frame mode are disabled. All bits of the transmitted service word are cleared. Spare bit values are cleared. No transparent mode active. XC0 XC1 00 H 9C H The transmit clock offset is cleared. The transmit time slot offset is cleared. RC0 RC1 00 H 9C H The receive clock slot offset is cleared. The receive time slot offset is cleared. IDLE ICB(4:1) 00 H 00 H Idle channel code is cleared. Normal operation (no “Idle Channel” selected). LIM0 LIM1 PCD PCR 00 H 00 H 00 H 00 H Slave Mode, local loop off Analog interface selected, remote loop off Pulse count for LOS detection cleared Pulse count for LOS recovery cleared XPM(2:0) 40 H, 03H, 7BH Transmit pulse mask (transmitter in tristate mode) IMR(5:0) FF H All interrupts are disabled RTR(4:1) TTR(4:1) TSS2 TSS3 all 00 H all 00 H 00 H 00 H No time slots selected GCR 00 H Internal second timer, power on CMR1 00 H RCLK output: DPLL clock, DCO-X enabled, DCO-X internal reference clock CMR2 00 H SCLKR selected, SCLKX selected, receive synchronization pulse sourced by SYPR, transmit synchronization pulse sourced by SYPX PC(4:1) 00 H, 00H 00 H, 00H Input function of ports RP(A to D): SYPR, Input function of ports XP(A to D): SYPX PC5 PC6 00 H 00 H SCLKR, SCLKX, RCLK configured to inputs, XMFS active low, CLK1 and CLK2 pin configuration MODE MODE2 MODE3 00 H 00 H 00 H Signaling controller disabled Table 46 Initial Values after Reset (E1) (cont’d) Register Reset Value Meaning |
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