PEB2256HT datasheet(188/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Operational Description E1

Data Sheet

188

2002-08-27

Operational Description E1

6.1

Operational Overview E1

The FALC56 can be operated in two modes, which are either E1 mode or T1/J1 mode.

The device is programmable via a microprocessor interface which enables byte or word

access to all control and status registers.

After reset the FALC56 must be initialized first. General guidelines for initialization are

described in Chapter 6.3.

The status registers are read-only and are updated continuously. Normally, the

processor reads the status registers periodically to analyze the alarm status and

signaling data.

6.2

Device Reset E1

The FALC56 is forced to the reset state if a low signal is input on pin RES for a minimum

period of 10 µs. During reset the FALC56 needs an active clock on pin MCLK. All output

stages are in a high-impedance state, all internal flip-flops are reset and most of the

control registers are initialized with default values.

SIgnals (for example RL1/2 receive line) should not be applied before the device is

powered up.

After reset the device is initialized to E1 operation.

6.3

Device Initialization in E1 Mode

After reset, the FALC56 is initialized for doubleframe format with register values listed in

the following table.

Table 46

Initial Values after Reset (E1)

Reset Value

Meaning

FMR0

NRZ Coding, no alarm simulation.

FMR1

FMR2

E1-doubleframe format, 2 Mbit/s system data rate, no AIS

transmission to remote end or system interface, payload

loop off.

SIC1

SIC2,

SIC3

8.192 MHz system clocking rate, receive buffer 2 frames,

transmit buffer bypass, data sampled or transmitted on the

falling edge of SCLKR/X, automatic freeze signaling, data

is active in the first channel phase

PEB2256HT Datasheet(PDF) 188 Page - Infineon Technologies AG

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