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PEB2256HT Datasheet(PDF) 192 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 192 Page - Infineon Technologies AG |
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192 / 490 page ![]() FALC56 V1.2 PEB 2256 Operational Description E1 Data Sheet 192 2002-08-27 helps to reduce the software load. They are very helpful especially to meet requirements as specified in ETS300 011. Table 49 Framer Initialization (E1) XSP.AXS = 1 ETS300 011 C4.x for instance requires the sending of E-Bits in TS0 if CRC4 errors have been detected. By programming XSP.AXS = 1 the submultiframe status is inserted automatically in the next outgoing multiframe. XSP.EBP = 1 If the FALC56 has reached asynchronous state the E-Bit is cleared if XSP.EBP = 0 and set if XSP.EBP = 1. ETS300 011 requires that the E-Bit is set in asynchronous state. FMR2.AXRA = 1 The transmission of RAI via the line interface is done automatically by the FALC56 in case of loss of frame alignment (FRS0.LFA = 1). If basic framing has been reinstalled RAI is automatically reset. FMR2.FRS(2:1) = 10 FMR1.AFR = 1 In this mode a search of double framing is automatically restarted, if no CRC4 multiframing is found within 8ms. Together with FMR2.AXRA = 1 this mode is essential to meet ETS300 011 and reduces the processor load heavily. FMR2.ALMF = 1 The receiver initiates a new basic- and multiframing research if more than 914 CRC4 errors have been detected in one second. FMR2.FRS1/0 = 11 In the interworking mode the FALC56 stays in double framing format if no multiframe pattern is found in a time interval of 400 ms. This is also indicated by a 400 ms interrupt. Additionally the extended interworking mode (FMR3.EXTIW = 1) will activate after 400 ms the remote alarm (FMR2.AXRA = 1) and will still search the multiframing without switching completely to the double framing. A complete resynchronization in an 8 ms interval is not initiated. Table 50 HDLC Controller Initialization (E1) MODE = 88 H MODE2= 88 H MODE3= 88 H HDLC channel 1 receiver active, no address comparison. HDLC channel 2 receiver active, no address comparison. HDLC channel 2 receiver active, no address comparison. CCR1 = 18 H CCR3= 08 H CCR4= 08 H Enable signaling via TS(31:0), interframe time fill with continuous flags (channel 1). Interframe time fill with continuous flags (channel 2). Interframe time fill with continuous flags (channel 3). |
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