PEB2256HT datasheet(193/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

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Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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FALC56 V1.2

PEB 2256

Operational Description E1

Data Sheet

193

2002-08-27

Note: After the device initialization a software reset should be executed by setting

of bits CMDR.XRES/RRES.

IMR0.RME = 0

IMR0.RPF = 0

IMR1.XPR = 0

IMR4.RME2=0

IMR4.RPF2=0

IMR5.XPR2=0

IMR5.RME3=0

IMR5.RPF3=0

IMR5.XPR3=0

Unmask interrupts for HDLC processor requests.

RTR3.TS16 = 1

TTR3.TS16 = 1

TSEO = 00

TSBS1 = FF

TSBS2= FF

TSBS3= FF

TSS2= 01

TSS3= 02

Select TS16 for HDLC data reception and transmission.

Even and odd frames are used for HDLC reception and

transmission.

Select all bits of selected time slot (channel 1).

Select all bits of selected time slot (channel 2).

Select all bits of selected time slot (channel 3).

Select time slot 1 for HDLC channel 2.

Select time slot 2 for HDLC channel 3.

Table 51

CAS-CC Initialization (E1)

XSP.CASEN = 1

CCR1.EITS = 0

Send CAS info stored in the XS(16:1) registers.

IMR0.CASC = 0

Enable interrupt with any data change in the RS(16:1) registers.

Table 50

HDLC Controller Initialization (E1) (cont’d)

PEB2256HT Datasheet(PDF) 193 Page - Infineon Technologies AG

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