PEB2256HT datasheet(197/490 Pages) INFINEON

197 / 490 page

FALC56 V1.2

PEB 2256

Operational Description T1/J1

Data Sheet

197

2002-08-27

Note: Read access to unused register addresses: value should be ignored.

Write access to unused register addresses: should be avoided, or set to “00”hex.

All control registers (except XFIFO, XS(12:1), CMDR, DEC) are of type read/write

Table 53

Initialization Parameters (T1/J1)

Basic Set Up

Master clocking mode

GCM(6:1) according to external MCLK clock frequency

T1/J1 mode select

FMR1.PMOD = 1,

RC0.SJR = 0

FMR1.PMOD = 1,

RC0.SJR = 1

Specification of line

interface and clock

generation

LIM0, LIM1, XPM(2:0)

Line interface coding

FMR0.XC(1:0), FMR0.RC(1:0)

Loss-of-signal detection/

recovery conditions

PCD, PCR, LIM1, LIM2

System clocking and data

rate

SIC1.SSC(1:0), SIC1.SSD1, FMR1.SSD0, CMR1.IRSP/

IRSC/IXSP/IXSC

Channel translation mode

FMR1.CTM

Transmit offset counters

XC0.XCO, XC1.XTO

Receive offset counters

RC0.RCO, RC1.RTO

AIS to system interface

FMR2.DAIS/SAIS

Operational Set Up

Select framing

FMR4.FM(1:0)

Framing additions

FMR1.CRC, FMR0.SRAF

Synchronization mode

FMR4.AUTO, FMR4.SSC(1:0), FMR2.MCSP,

FMR2.SSP

Signaling mode

FMR5.EIBR, XC0.BRM, MODE, MODE2, MODE3,

CCR1, CCR2, RAH(2:1), RAL(2:1)

PEB2256HT Datasheet(PDF) 197 Page - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 197 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL