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PEB2256HT Datasheet(PDF) 198 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 198 Page - Infineon Technologies AG |
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198 / 490 page ![]() FALC56 V1.2 PEB 2256 Operational Description T1/J1 Data Sheet 198 2002-08-27 Specific T1/J1 Initialization The following is a suggestion for a basic initialization to meet most of the T1/J1 requirements. Depending on different applications and requirements any other initialization can be used. Table 54 Line Interface Initialization (T1/J1) Register Function FMR0.XC0/1 FMR0.RC0/1 LIM1.DRS CCB(3:1) SIC3.CMI The FALC56 supports requirements for the analog line interface as well as the digital line interface. For the analog line interface the codes AMI (with and without bit 7stuffing) and B8ZS are supported. For the digital line interface modes (dual- or single-rail) the FALC56 supports AMI (with and without bit 7 stuffing), B8ZS (with and without B8ZS precoding) and NRZ. PCD = 0A H LOS detection after 176 consecutive “zeros” (fulfills G.775/ Telcordia (Bellcore)/AT&T) PCR = 15 H LOS recovery after 22 “ones” in the PCD interval (fulfills G.775, Bellcore/AT&T). LIM1.RIL(2:0) =02 H LOS threshold of 0.6 V (fulfills G.775). GCR.SCI = 1 Additional Recovery Interrupts. Help to meet alarm activation and deactivation conditions in time. LIM2.LOS1 = 1 Automatic pulse-density check on 15 consecutive zeros for LOS recovery condition (Bellcore requirement) |
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