PEB2256HT datasheet(201/490 Pages) INFINEON

201 / 490 page

FALC56 V1.2

PEB 2256

Signaling Controller Operating Modes

Data Sheet

201

2002-08-27

Signaling Controller Operating Modes

The three HDLC controllers can be programmed to operate in various modes, which are

different in the treatment of the HDLC frame in receive direction. Thus, the receive data

flow and the address recognition features can be performed in a very flexible way, to

satisfy almost any practical requirements.

There are 4 different operating modes which can be set via the mode registers (MODE,

MODE2 and MODE3).

If not mentioned otherwise, all functions described for HDLC channel 1 apply to channel

2 and 3 as well.

8.1

HDLC Mode

All frames with valid addresses are forwarded directly via the RFIFO to the system

memory.

Depending on the selected address mode, the FALC56 can perform a 1- or 2-byte

address recognition (MODE.MDS0).

If a 2-byte address field is selected, the high address byte is compared to the fixed value

FEH or FCH (group address) as well as with two individually programmable values in

RAH1 and RAH2 registers. According to the ISDN LAPD protocol, bit 1 of the high byte

address is interpreted as command/response bit (C/R) and is excluded from the address

comparison.

Similarly, two compare values can be programmed in special registers (RAL1, RAL2) for

the low address byte. A valid address is recognized in case the high and low byte of the

address field correspond to one of the compare values. Thus, the FALC56 can be called

(addressed) with 6 different address combinations. HDLC frames with address fields that

do not match any of the address combinations, are ignored by the FALC56.

In case of a 1-byte address, RAL1 and RAL2 are used as compare registers. The HDLC

control field, data in the I-field and an additional status byte are temporarily stored in the

RFIFO. Additional information can also be read from a special register (RSIS).

As defined by the HDLC protocol, the FALC56 performs the zero bit insertion/deletion

(bit stuffing) in the transmit/receive data stream automatically. That means, it is

guaranteed that at least one “0” will appear after 5 consecutive “1”s.

8.1.1

Non-Auto Mode

(MODE.MDS(2:1) = 01; MODE2.MDS22..21=01; MODE3.MDS32..31=01)

Characteristics: address recognition, flag- and CRC generation/check, bit stuffing

All frames with valid addresses are forwarded directly via the RFIFO (RFIFO2, RFIFO3)

to the system memory.

PEB2256HT Datasheet(PDF) 201 Page - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 201 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL