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PEB2256HT Datasheet(PDF) 204 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 204 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
Signaling Controller Operating Modes
Data Sheet
204
2002-08-27
8.1.6
Transmit Data Flow
The frames can be transmitted as shown below.
Figure 77
HDLC Transmit Data Flow
Transmitting a HDLC frame via register CMDR.XTF (or CMDR2.XTF2/CMDR3.XTF3 for
channel 2/3), the address, the control fields and the data field have to be entered in the
XFIFO (XFIFO2, XFIFO3).
If CCR2.XCRC (or CCR3.XCRC2/CCR4.XCRC3 for channel 2/3) is set, the CRC
checksum will not be generated internally. The checksum has to be provided via the
transmit FIFO (XFIFO, XFIFO2, XFIFO3) as the last two bytes. The transmitted frame is
closed automatically with a closing flag only.
The FALC56 does not check whether the length of the frame, i.e. the number of bytes to
be transmitted makes sense or not.
8.2
Extended Transparent Mode
Characteristics: fully transparent
In no HDLC mode, fully transparent data transmission/reception without HDLC framing
is performed, i.e. without flag generation/recognition, CRC generation/check, or bit
stuffing. This feature can be profitably used e.g. for:
• Specific protocol variations
• Transmission of a BOM frame (channel 1 only)
• Test purposes
Data transmission is always performed out of the XFIFO (XFIFO2, XFIFO3). In
transparent mode, the receive data is shifted into the RFIFO (RFIFO2, RFIFO3).
Note: If a 1-byte frame is sent in extended transparent mode, in addition to interrupt
ISR1.XPR (transmit pool ready) the interrupt ISR1.XDU (transmit buffer underrun)
is set and XFIFO is blocked.
CONTROL
(XHF)
Frame
HDLC
Transmit
ADDRESS
FLAG
XFIFO
ADDR
CTRL
FLAG
DATA
Ι
CHECKRAM
ITD06456
CRC



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