PEB2256HT datasheet(208/490 Pages) INFINEON

208 / 490 page

FALC56 V1.2

PEB 2256

Signaling Controller Operating Modes

Data Sheet

208

2002-08-27

8.3.5

HDLC Data Reception

×32 byte FIFO buffers are also provided in receive direction for each HDLC channel.

There are different interrupt indications concerned with the reception of data:

• RPF (RPF2, RPF3, receive pool full) interrupt, indicating that a 32-byte block of data

can be read from RFIFO (RFIFO2, RFIFO3) and the received message is not yet

complete.

• RME (RME2, RME3, receive message end) interrupt, indicating that the reception of

one message is completed.

The following figure gives an example of a reception sequence, assuming that a “long”

frame (66 bytes) followed by two short frames (6 bytes each) are received.

Figure 80

Interrupt Driven Reception Sequence Example

8.3.6

a-bit Access (E1)

The FALC56 supports the S

a-bit signaling of time slot 0 of every other frame as follows:

• Access via registers RSW/XSW

• Access via registers RSA(8:4)/XSA(8:4)

capable of storing the information for a complete multiframe

• Access via the 64 byte deep receive/transmit FIFO of the integrated signaling

controller (HDLC channel 1 only). This S

a-bit access gives the opportunity to transmit/

receive a transparent bit stream as well as HDLC frames where the signaling

controller automatically processes the HDLC protocol. Enabling is done by setting of

bit CCR1.EITS and resetting of registers TTR(4:1), RTR(4:1) and FMR1.ENSA.

ITD10972

RD RFIFO

32 bytes

RMC

Receive Frame 1 (66 bytes)

RPF

32 bytes

RD RFIFO

RMC

RME

RMC

RME

RMC

RF2 RF3

FALC

Interface

CPU

Interface

System

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