PEB2256HT datasheet(211/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

Scroll/Zoom	100%

Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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211 / 490 page

FALC56 V1.2

PEB 2256

Signaling Controller Operating Modes

Data Sheet

211

2002-08-27

8.3.8

Data Link Access in ESF/F72 Format (T1/J1)

The FALC56 supports the DL-channel protocol using the ESF or F72 (SLC96) format as

follows (HDLC channel 1 only):

• Sampling of DL-bits is done on a multiframe basis and stored in the registers

RDL(3:1). A receive multiframe begin interrupt is provided to read the received data

DL-bits. The contents of registers XDL(3:1) is subsequently sent out on the transmit

multiframe basis if it is enabled via FMR1.EDL. A transmit multiframe begin interrupt

requests for writing new information to the DL-bit registers.

• If enabled via CCR1.EDLX/EITS = 10, the DL-bit information is stored in the receive

FIFO of the signaling controller. The DL-bits stored in the XFIFO are inserted into the

outgoing data stream. If CCR1.EDLX is cleared, a HDLC frame or a transparent frame

can be sent or received via the RFIFO/XFIFO.

PEB2256HT Datasheet(PDF) 211 Page - Infineon Technologies AG