PEB2256HT datasheet(202/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

Scroll/Zoom	100%

Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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202 / 490 page

FALC56 V1.2

PEB 2256

Signaling Controller Operating Modes

Data Sheet

202

2002-08-27

8.1.2

Transparent Mode 1

(MODE.MDS(2:0) = 101; MODE2.MDS2(2:0)=101; MODE3.MDS3(2:0)=101)

Characteristics: address recognition, flag- and CRC generation/check, bit stuffing

Only the high byte of a 2-byte address field is compared to registers RAH(2:1). The

whole frame excluding the first address byte is stored in RFIFO (RFIFO2, RFIFO3).

8.1.3

Transparent Mode 0

(MODE.MDS(2:0) = 100; MODE2.MDS2(2:0)=100; MODE3.MDS3(2:0)=100)

Characteristics: flag- and CRC generation/check, bit stuffing

No address recognition is performed and each frame is stored in the RFIFO (RFIFO2,

RFIFO3).

8.1.4

SS7 Support

SS7 protocol is supported for channel 1 only by means of several hardware features as

described in Chapter 4.1.14.2 on page 74 and Chapter 5.1.14.2 on page 135.

8.1.5

Receive Data Flow

The following figure gives an overview of the management of the received HDLC frames

in the different operating modes.

PEB2256HT Datasheet(PDF) 202 Page - Infineon Technologies AG