PEB2256HT datasheet(200/490 Pages) INFINEON

200 / 490 page

FALC56 V1.2

PEB 2256

Operational Description T1/J1

Data Sheet

200

2002-08-27

Note: After the device initialization a software reset should be executed by setting of bits

CMDR.XRES/RRES.

Table 56

HDLC Controller Initialization (T1/J1)

MODE = 88

MODE2= 88

MODE3= 88

HDLC channel 1 receiver active, no address comparison.

HDLC channel 2 receiver active, no address comparison.

CCR1 = 18

CCR3= 08

CCR4= 08

Enable signaling via TS(24:1), interframe time fill with continuous

flags (channel 1).

Interframe time fill with continuous flags (channel 2).

Interframe time fill with continuous flags (channel 3).

IMR0.RME = 0

IMR0.RPF = 0

IMR1.XPR = 0

IMR4.RME2=0

IMR4.RPF2=0

IMR5.XPR2=0

IMR5.RME3=0

IMR5.RPF3=0

IMR5.XPR3=0

Unmask interrupts for HDLC processor requests.

RTR4.0 = 1

TTR4.0 = 1

TSEO = 00

TSBS1 = FF

TSBS2= FF

TSBS3= FF

TSS2= 01

TSS3= 02

Select time slot 24 for HDLC data reception and transmission.

Even and odd frames are used for HDLC reception and

transmission.

Select all bits of selected time slot (channel 1).

Select all bits of selected time slot (channel 2).

Select all bits of selected time slot (channel 3).

Select time slot 1 for HDLC channel 2.

Select time slot 2 for HDLC channel 3.

Table 57

Initialization of the CAS-BR Controller (T1/J1)

FMR5.EIBR = 1

Enable CAS-BR Mode

Send CAS-BR information stored in XS(12:1)

IMR1.CASE = 0

IMR0.RSC = 0

Enable interrupts which indicate the access to the XS(12:1) CAS-

BR registers and any data change in RS(12:1)

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