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PEB2256HT Datasheet(PDF) 217 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 217 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
E1 Registers
Data Sheet
217
2002-08-27
9.2
Detailed Description of E1 Control Registers
Transmit FIFO - HDLC Channel 1 (Write)
Writing data to XFIFO of HDLC channel 1 can be done in 8-bit (byte) or 16-bit (word)
access. The LSB is transmitted first.
Up to 32 bytes/16 words of transmit data can be written to the XFIFO following a XPR
interrupt.
Command Register (Write)
Value after reset: 00
H
RMC
Receive Message Complete - HDLC Channel 1
Confirmation from CPU to FALC56 that the current frame or data
block has been fetched following a RPF or RME interrupt, thus the
occupied space in the RFIFO can be released. If RMC is given while
RFIFO is already cleared, the next incoming data block is cleared
instantly, although interrupts are generated.
RRES
Receiver Reset
The receive line interface except the clock and data recovery unit
(DPLL), the receive framer, the one-second timer and the receive
signaling controller are reset. However the contents of the control
registers is not deleted.
XREP
Transmission Repeat - HDLC Channel 1
If XREP is set together with XTF (write 24
H to CMDR), the FALC56
repeatedly transmits the contents of the XFIFO (1 to 32 bytes) without
HDLC framing fully transparently, i.e. without flag, CRC.
The cyclic transmission is stopped with a SRES command or by
resetting XREP.
Note:During cyclic transmission the XREP-bit has to be set with
every write operation to CMDR.
70
XFIFO
XF7
XF0
(00)
XFIFO
XF15
XF8
(01)
70
CMDR
RMC
RRES
XREP
XRES
XHF
XTF
XME
SRES
(02)



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