PEB2256HT datasheet(219/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

Scroll/Zoom	100%

Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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219 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

219

2002-08-27

Mode Register (Read/Write)

Value after reset: 00

MDS(2:0)

Mode Select - HDLC Channel 1

The operating mode of the HDLC controller is selected.

000 = Reserved

001 = Signaling System 7 (SS7) support

010 = One-byte address comparison mode (RAL1,2)

011 = Two-byte address comparison mode (RAH1,2 and RAL1,2)

100 = No address comparison

101 = One-byte address comparison mode (RAH1,2)

110 = Reserved

111 = No HDLC framing mode

HRAC

Receiver Active - HDLC Channel 1

Switches the HDLC receiver to operational or inoperational state.

0 =

Receiver inactive

1 =

Receiver active

DIV

Data Inversion - HDLC Channel 1

Setting this bit inverts the internal generated HDLC channel 1 data

stream.

= Normal operation, HDLC data stream not inverted

= HDLC data stream inverted

MODE

MDS2

MDS1

MDS0

HRAC

DIV

(03)

CCR2.RADD must be set, if SS7 mode is selected

PEB2256HT Datasheet(PDF) 219 Page - Infineon Technologies AG