PEB2256HT datasheet(222/490 Pages) INFINEON

222 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

222

2002-08-27

Determines the synchronization mode of the channel associated

signaling multiframe alignment.

0 =

Synchronization is done in accordance to ITU-T G. 732

1 =

Synchronization is established when two consecutively correct

multiframe alignment pattern are found.

EITS

Enable Internal Time Slot 0 to 31 Signaling

0 =

Internal signaling in time slots 0 to 31 defined by registers

RTR(4:1) or TTR(4:1) is disabled.

1 =

Internal signaling in time slots 0 to 31 defined by registers

RTR(4:1) or TTR(4:1) is enabled.

ITF

Interframe Time Fill

Determines the idle (= no data to be sent) state of the transmit data

coming from the signaling controller.

0 =

Continuous logical "1" is output

1 =

Continuous flag sequences are output ("01111110" bit

patterns)

XMFA

Transmit Multiframe Aligned

Determines the synchronization between the framer and the

corresponding signaling controller.

0 =

The contents of the XFIFO is transmitted without multiframe

alignment.

1 =

The contents of the XFIFO is transmitted multiframe aligned.

The first byte in XFIFO is transmitted in the first time slot

selected by TTR(4:1) and so on.

After reception of a complete multiframe in the time slot mode

(RTR(4:1)) an ISR0.RME interrupt is generated, if no HDLC

mode is enabled

In S

a-bit access mode XMFA is not valid.

Note: During the transmission of the XFIFO content, the SYPX or

XMFS interval time should not be changed, otherwise the

XFIFO data has to be retransmitted.

PEB2256HT Datasheet(PDF) 222 Page - Infineon Technologies AG

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