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PEB2256HT Datasheet(PDF) 225 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 225 Page - Infineon Technologies AG |
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225 / 490 page ![]() FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 225 2002-08-27 Receive Time Slot Register 1 to 4 (Read/Write) Value after reset: 00 H, 00H, 00H, 00H TS(31:0) Time Slot These bits define the received time slots on the system highway port RDO to be extracted to RFIFO and marked. Additionally these registers control the RSIGM marker which can be forced high during the corresponding time slots independently of bit CCR1.EITS. A one in the RTR(4:1) bits samples the corresponding time slots and send their data to the RFIFO of the signaling controller if bit CCR1.EITS is set. Assignments: TS0 →Time slot 0 ... TS31 → Time slot 31 0 =The corresponding time slot is not extracted and stored into the RFIFO. 1 = The contents of the selected time slot is stored in the RFIFO. Although the idle time slots can be selected. This function is activated, if bit CCR1.EITS is set. The corresponding time slot is forced high on marker pin RSIGM. 70 RTR1 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 (0C) RTR2 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 (0D) RTR3 TS16 TS17 TS18 TS19 TS20 TS21 TS22 TS23 (0E) RTR4 TS24 TS25 TS26 TS27 TS28 TS29 TS30 TS31 (0F) |
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