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PEB2256HT Datasheet(PDF) 227 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 227 Page - Infineon Technologies AG |
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227 / 490 page  FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 227 2002-08-27 Interrupt Mask Register 0 to 5 (Read/Write) Value after reset: FF H, FFH, FFH, FFH, FFH IMR(5:0) Interrupt Mask Register Each interrupt source can generate an interrupt signal on port INT (characteristics of the output stage are defined by register IPC). A “1” in a bit position of IMR(5:0) sets the mask active for the interrupt status in ISR(5:0). Masked interrupt statuses neither generate a signal on INT, nor are they visible in register GIS. Moreover, they are - not displayed in the interrupt status register if bit GCR.VIS is cleared - displayed in the interrupt status register if bit GCR.VIS is set Note: After reset, all interrupts are disabled. Single Bit Defect Insertion Register (Read/Write) Value after reset: 00 H After setting the corresponding bit, the selected defect is inserted into the transmit data stream at the next possible position. After defect insertion is completed, the bit is reset automatically. IFASE Insert single FAS defect IMFE Insert single multiframe defect ICRCE Insert single CRC defect ICASE Insert single CAS defect IPE Insert single PRBS defect 70 IMR0 RME RFS T8MS RMB CASC CRC4 SA6SC RPF (14) IMR1 LLBSC RDO ALLS XDU XMB SUEX XLSC XPR (15) IMR2 FAR LFA MFAR T400MS AIS LOS RAR RA (16) IMR3 ES SEC LMFA16 AIS16 RA16 RSN RSP (17) IMR4 XSP XSN RME2 RFS2 RDO2 ALLS2 XDU2 RPF2 (18) IMR5 XPR2 XPR3 RME3 RFS3 RDO3 ALLS3 XDU3 RPF3 (19) IERR IFASE IMFE ICRCE ICASE IPE IBV (1B) |
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