PEB2256HT datasheet(231/490 Pages) INFINEON

231 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

231

2002-08-27

1 =

PCM 24 or T1/J1 mode (see RC0.SJR for T1/J1 selection).

XFS

Transmit Framing Select

Selection of the transmit framing format can be done independently

of the receive framing format.

0 =

Doubleframe format enabled.

1 =

CRC4-multiframe format enabled.

ECM

Error Counter Mode

The function of the error counters is determined by this bit.

0 =

Before reading an error counter the corresponding bit in the

Disable Error Counter register (DEC) has to be set. In 8 bit

access the low byte of the error counter should always be read

before the high byte. The error counters are reset with the rising

edge of the corresponding bits in the DEC register.

1 =

Every

second

the

error

counter

latched

and

then

automatically reset. The latched error counter state should be

read within the next second. Reading the error counter during

updating should be avoided (do not access an error counter

within 1 µs after the one-second interrupt occurs).

SSD0

Select System Data Rate 0

FMR1.SSD0 and SIC1.SSD1 define the data rate on the system

highway. Programming is done with SSD1/SSD0 in the following

table.

00 = 2.048 Mbit/s

01 = 4.096 Mbit/s

10 = 8.192 Mbit/s

11 = 16.384 Mbit/s

XAIS

Transmit AIS Towards Remote End

Sends AIS on ports XL1, XL2, XOID towards the remote end. The

outgoing data stream which can be looped back through the local loop

to the system interface is not affected.

PEB2256HT Datasheet(PDF) 231 Page - Infineon Technologies AG

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