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PEB2256HT Datasheet(PDF) 230 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 230 Page - Infineon Technologies AG |
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230 / 490 page  FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 230 2002-08-27 Framer Mode Register 1 (Read/Write) Value after reset: 00 H MFCS Multiframe Force Resynchronization Only valid if CRC multiframe format is selected (FMR2.RFS(1:0) = 10). A transition from low to high initiates the resynchronization procedure for CRC-multiframe alignment without influencing doubleframe synchronous state. In case, “Automatic Force Resynchronization” (FMR1.AFR) is enabled and multiframe alignment cannot be regained, a new search of doubleframe (and CRC multiframe) is automatically initiated. AFR Automatic Force Resynchronization Only valid if CRC multiframe format is selected (FMR2.RFS(1:0) = 10). If this bit is set, a search of doubleframe alignment is automatically initiated if two multiframe patterns with a distance of n × 2ms have not been found within a time interval of 8 ms after doubleframe alignment has been regained or command FMR1.MFCS has been issued. ENSA Enable Sa-Bit Access through Register XSA4-8 Only applicable if FMR1.XFS is set. 0 = Normal operation. The S a-bit information is taken from bits XSW.XY(4:0) and written to bits RSW.RY(4:0). 1= S a-bit register access. The Sa-bit information is taken from the registers XSA(8:4). In addition, the received information is written to registers RSA(8:4). Transmitting of the contents of registers XSA(8:4) is disabled if one of time slot 0 transparent modes is enabled (XSP.TT0 or TSWM.SA(8:4)). PMOD PCM Mode For E1 application this bit must be set low. Switching from E1 to T1 or vice versa the device needs up to 20 µs to settle up to the internal clocking. 0 = PCM 30 or E1 mode. 70 FMR1 MFCS AFR ENSA PMOD XFS ECM SSD0 XAIS (1D) |
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