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PEB2256HT Datasheet(PDF) 233 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 233 Page - Infineon Technologies AG |
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233 / 490 page  FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 233 2002-08-27 immediately on port RDO by setting the FMR2.SAIS bit. It is recommended to write the actual value of XC1 into this register once again, because a write access to register XC1 sets the read/write pointer of the transmit elastic buffer into its optimal position to ensure a maximum wander compensation (the write operation forces a slip). AXRA Automatic Transmit Remote Alarm 0 = Normal operation 1 = The remote alarm bit is set automatically in the outgoing data stream if the receiver is in asynchronous state (FRS0.LFA bit is set). In synchronous state the remote alarm bit is reset. Additionally in multiframe format FMR2.RFS1 = 1 and FMR3.EXTIW = 1 and the 400 ms time-out has elapsed, the remote alarm bit is active in the outgoing data stream. In multiframe synchronous state the outgoing remote alarm bit is cleared. ALMF Automatic Loss of Multiframe 0 = Normal operation 1 = The receiver searches a new basic- and multiframing if more than 914 CRC errors have been detected in a time interval of one second. The internal 914 CRC error counter is reset if the multiframe synchronization is found. Incrementing the counter is only enabled in the multiframe synchronous state. Channel Loop-Back (Read/Write) Value after reset: 00 H ECLB Enable Channel Loop-Back 0 = Disables the channel loop-back. 1 = Enables the channel loop-back selected by this register. CLA(4:0) Channel Address For Loop-Back CLA = 0 to 31 selects the channel. During looped back the contents of the assigned outgoing channel on ports XL1/XDOP/XOID and XL2/XDON is equal to the idle channel code programmed at register IDLE. 70 LOOP ECLB CLA4 CLA3 CLA2 CLA1 CLA0 (1F) |
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