PEB2256HT datasheet(237/490 Pages) INFINEON

237 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

237

2002-08-27

direction together with these bits the TSWM.TSA(8:4) bits must

be set to enable transmission to the remote end transparently

through the FALC56.

XCO(10:8)

Transmit Offset

Initial value loaded into the transmit bit counter at the trigger edge of

SCLKX when the synchronous pulse on port SYPX/XMFS is active

Refer to register XC1.

Transmit Control 1 (Read/Write)

Value after reset: 9C

A write access to this address resets the transmit elastic buffer to its

basic starting position. Therefore, updating the value should only be

done when the FALC56 is initialized or when the buffer should be

centered. As a consequence a transmit slip will occur.

XCO(7:0)

Transmit Offset

Calculation of delay time T (SCLKX cycles) depends on the value X

of the “Transmit Offset” register XC(1:0):

≤ T ≤ 4: X = 4 - T

≤ T ≤ maximum delay: X = 256 × SC/SD - T + 4)

with maximum delay = (256

× SC/SD) -1

with SC = system clock defined by SIC1.SSC(1:0)

with SD = 2.048 MHz

Delay time T = time between beginning of time slot 0 (bit 0, channel

phase 0) at XDI/XSIG and the initial edge of SCLKX after SYPX/

XMFS goes active.

See page 111 for further description.

XC1

XCO7

XCO0

(23)

PEB2256HT Datasheet(PDF) 237 Page - Infineon Technologies AG