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PEB2256HT Datasheet(PDF) 239 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 239 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
E1 Registers
Data Sheet
239
2002-08-27
RCO(10:8)
Receive Offset/Receive Frame Marker Offset
Depending on the RP(A to D) pin function different offsets can be
programmed. The SYPR and the RFM pin function cannot be
selected in parallel.
Receive Offset (PC(4:1).RPC(2:0) = 000)
Initial value loaded into the receive bit counter at the trigger edge of
SCLKR when the synchronous pulse on port SYPR is active.
Calculation of delay time T (SCLKR cycles) depends on the value X
of the receive offset register RC(1:0). For programing refer to register
RC1.
Receive Frame Marker Offset (PC(4:1).RPC(2:0) = 001
B)
Offset programming of the receive frame marker which is output on
port SYPR. The receive frame marker can be activated during any bit
position of the current frame.
Calculation of the value X of the receive offset register RC(1:0)
depends on the bit position which should be marked and SCLKR.
Refer to register RC1.
Receive Control 1 (Read/Write)
Value after reset: 9C
H
RCO(7:0)
Receive Offset/Receive Frame Marker Offset
Depending on the RP(A to D) pin function different offsets can be
programmed. The SYPR and the RFM pin function cannot be
selected in parallel.
Receive Offset (PC(4:1).RPC(2:0) = 000)
Initial value loaded into the receive bit counter at the trigger edge of
SCLKR when the synchronous pulse on port SYPR is active.
Calculation of delay time T (SCLKR cycles) depends on the value X
of the receive offset register RC(1:0):
0
≤ T ≤ 4: X = 4 - T
5
≤ T ≤ maximum delay:X = 2052 - T
with maximum delay = (256
×SC/SD) -1
with SC = system clock defined by SIC1.SSC(1:0)
with SD = system data rate
70
RC1
RCO7
RCO0
(25)



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