 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PEB2256HT Datasheet(PDF) 243 Page - Infineon Technologies AG |
|
|
|||||||||||||||||||||||||||||
PEB2256HT Datasheet(HTML) 243 Page - Infineon Technologies AG |
|
|
243 / 490 page  FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 243 2002-08-27 TSA(8:4) Transparent S a(8:4)-Bit 0 = The S a(8:4)-bits are generated internally. 1 = The S a(8:4)-bits are taken from port XDI or from the internal signaling controller if enabled and transparently passed through the FALC56 without any changes. The internal information of the FALC56 (registers XSW and XSA(8:4)) is ignored. Idle Channel Code Register (Read/Write) Value after reset: 00 H IDL(7:0) Idle Channel Code If channel loop-back is enabled by programming LOOP.ECLB = 1, the contents of the assigned outgoing channel on ports XL1/XL2 or XDOP/XDON is set equal to the idle channel code selected by this register. Additionally, the specified pattern overwrites the contents of all channels selected by the idle channel registers ICB(4:1). IDL7 is transmitted first. 70 IDLE IDL7 IDL0 (2B) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
