PEB2256HT datasheet(244/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

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Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

244

2002-08-27

Transmit S

a(8:4) Register (Read/Write)

Value after reset: 00

H, 00H, 00H, 00H, 00H

XSA(8:4)

Transmit Sa-Bit Data

The S

a-bit register access is enabled by setting bit FMR1.ENSA = 1.

With the transmit multiframe begin an interrupt ISR1.XMB is

generated and the contents of these registers XSA(8:4) is copied into

a shadow register. The contents is subsequently sent out in the

service words of the next outgoing CRC multiframe (or doubleframes)

if none of the time slot 0 transparent modes is enabled. XS40 is sent

out in bit position 4 in frame 1, XS47 in frame 15. The transmit

multiframe begin interrupt XMB request that these registers should be

serviced. If requests for new information are ignored, current contents

is repeated.

XSA4

XS47

XS46

XS45

XS44

XS43

XS42

XS41

XS40

(2C)

XSA5

XS57

XS56

XS55

XS54

XS53

XS52

XS51

XS50

(2D)

XSA6

XS67

XS66

XS65

XS64

XS63

XS62

XS61

XS60

(2E)

XSA7

XS77

XS76

XS75

XS74

XS73

XS72

XS71

XS70

(2F)

XSA8

XS87

XS86

XS85

XS84

XS83

XS82

XS81

XS80

(30)

PEB2256HT Datasheet(PDF) 244 Page - Infineon Technologies AG

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