PEB2256HT datasheet(245/490 Pages) INFINEON

245 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

245

2002-08-27

Framer Mode Register 3 (Read/Write)

Value after reset: 00

XLD

Transmit LLB Down Code

0 =

Normal operation.

1 =

A one in this bit position causes the transmitter to replace

normal transmit data with the LLB down (deactivate) Code

continuously until this bit is reset. The LLB down Code is

optionally overwritten by the time slot 0 depending on bit

LCR1.FLLB.

XLU

Transmit LLB UP Code

0 =

Normal operation.

1 =

A one in this bit position causes the transmitter to replace

normal transmit data with the LLB UP Code continuously until

this bit is reset. The LLB UP Code is overwritten by the time slot

0 depending on bit LCR1.FLLB. For proper operation bit

FMR3.XLD must be cleared.

CMI

Select CMI Precoding

Only valid if CMI code (FMR0.XC(1:0) = 01) is selected. This bit

defines the CMI precoding and influences transmit and receive data.

0 =

CMI with HDB3 precoding

1 =

CMI without HDB3 precoding

Note: Before local loop is selected, HDB3 precoding has to be

disabled.

SA6SY

Receive S

a6-Access Synchronous Mode

Only valid if multiframe format (FMR2.RFS(1:0) = 1x) is selected.

0 =

The detection of the predefined S

a6-bit pattern (refer to chapter

a6-bit

detection

according

ETS

300233)

done

independently of the multiframe synchronous state.

1 =

The detection of the S

a6-bit pattern is done synchronously to

the multiframe.

FMR3

XLD

XLU

CMI

SA6SY

EXTIW

(31)

PEB2256HT Datasheet(PDF) 245 Page - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 245 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL