PEB2256HT datasheet(249/490 Pages) INFINEON

249 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

249

2002-08-27

JATT, RL

Remote Loop Transmit Jitter Attenuator

00 = Normal operation. The remote loop transmit jitter attenuator is

disabled. Transmit data bypasses the remote loop jitter

attenuator buffer.

01 = Remote loop active without remote loop transmit jitter

attenuator enabled. Transmit data bypasses the remote loop

jitter attenuator buffer.

10 = not defined

11 = Remote loop and remote loop jitter attenuator active. Received

data from pins RL1/2 or RDIP/N or ROID is sent "jitter-free" on

ports XL1/2 or XDOP/N or XOID. The de-jittered clock is

generated by the DCO-X circuitry.

Note: JATT is only used to define the jitter attenuation during remote

loop operation. Jitter attenuation during normal operation is

not affected.

DRS

Dual-Rail Select

0 =

The ternary interface is selected. Multifunction ports RL1/2 and

XL1/2 become analog in/outputs.

1 =

The digital dual-rail interface is selected. Received data is

latched on multifunction ports RDIP/RDIN while transmit data is

output on pins XDOP/XDON.

Pulse Count Detection Register (Read/Write)

Value after reset: 00

PCD(7:0)

Pulse Count Detection

A LOS alarm is detected if the incoming data stream has no

transitions for a programmable number T consecutive pulse

positions. The number T is programmable by the PCD register and

can be calculated as follows:

T=16

× (N+1); with 0 ≤ N ≤ 255.

The maximum time is: 256

× 16 × 488 ns = 2 ms. Every detected

pulse resets the internal pulse counter. The counter is clocked with

the receive clock RCLK.

PCD

PCD7

PCD0

(38)

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