PEB2256HT datasheet(248/490 Pages) INFINEON

248 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

248

2002-08-27

undisturbedly on the line. Receiver and transmitter coding must

be identical. Operates in analog and digital line interface mode.

In analog line interface mode data is transferred through the

complete analog receiver.

MAS

Master Mode

0 =

Slave mode

1 =

Master mode on. Setting this bit the DCO-R circuitry is

frequency synchronized to the clock (2.048 MHz or 8 kHz, see

IPC.SSYF) supplied by SYNC. If this pin is connected to V

SS or

DD (or left open and pulled up to VDD internally) the DCO-R

circuitry is centered and no receive jitter attenuation is

performed (only if 2.048 MHz clock is selected by resetting bit

IPC.SSYF). The generated clocks are stable.

Line Interface Mode 1 (Read/Write)

Value after reset: 00

CLOS =

Clear data in case of LOS

0 =

Normal receiver mode, receive data stream is transferred

normally in long-haul mode

1 =

In long-haul mode received data is cleared (driven to low level),

as soon as LOS is detected

RIL(2:0)

Receive Input Threshold

Only valid if analog line interface is selected (LIM1.DRS = 0).

“No signal” is declared if the voltage between pins RL1 and RL2 drops

below the limits programmed by bits RIL(2:0) and the received data

stream has no transition for a period defined in the PCD register.

The threshold where “no signal” is declared is programmable by the

RIL(2:0) bits depending on bit LIM0.EQON.

Note: LIM1.RIL(2:0) must be programmed before LIM0.EQON = 1 is

set.

See DC characteristics for detail.

LIM1

CLOS

RIL2

RIL1

RIL0

JATT

DRS

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PEB2256HT Datasheet(PDF) 248 Page - Infineon Technologies AG

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